clk: mediatek: mt8188: refactor driver to improve readability

clk: mediatek: mt8188: refactor driver to improve readability

Refactor some part of the driver to improve readability and future
additions:

- use CLK_TOP_NR_CLK for added clocks
- rename the id map to make it more clear that the map applies to top
  clocks only
- refactor the id map to improve readability
- xtal2_rate is only used for PLL clocks, so only the apmixedsys clock
  tree needs it. Remove it elsewhere.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>