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arm64: versal-net: Describe L1/L2/L3/LLC caches
authorMichal Simek <michal.simek@amd.com>
Mon, 8 Sep 2025 13:33:48 +0000 (15:33 +0200)
committerMichal Simek <michal.simek@amd.com>
Wed, 10 Sep 2025 13:56:24 +0000 (15:56 +0200)
commit0e81960419ad186378b4cb55d7939d03c85262ab
tree2dbeb70982ea8ae1972e0dedb2dee2aaa123d64ftree | snapshot
parent21ad89cfade7724960a02ce675f6cd33f89515edcommit | diff
arm64: versal-net: Describe L1/L2/L3/LLC caches

Add missing cache layout description.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f740bf2d0af1e7e50d76196ec050c0fdbeceb049.1757338426.git.michal.simek@amd.com
arch/arm64/boot/dts/xilinx/versal-net.dtsi diff | blob | blame | history
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