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ARM: dts: socfpga: update NAND clocking for c5/a5
authorDinh Nguyen <dinguyen@kernel.org>
Mon, 9 Jul 2018 22:16:00 +0000 (17:16 -0500)
committerDinh Nguyen <dinguyen@kernel.org>
Thu, 30 Aug 2018 13:38:26 +0000 (08:38 -0500)
commit0ffc5df823dd3495441c47ea3ffaa09d4a57a5f1
tree69b2f5a5295dec4d8057f722e54874a8bd1eadd7tree | snapshot
parent12b2982a1f72ce453d76da977e1dad422b2f34adcommit | diff
ARM: dts: socfpga: update NAND clocking for c5/a5

The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). The
nand_x_clk and nand_ecc_clk are derived from the nand_clk. The nand_x_clk
has a fixed divider of 4.

Also, update the NAND dts property with the correct clocks property.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: add nand_ecc_clk and update commit message
arch/arm/boot/dts/socfpga.dtsi diff | blob | blame | history
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