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riscv: cpu: th1520: Limit upper RAM boundary to 4 GiB
authorYao Zi <ziyao@disroot.org>
Thu, 10 Jul 2025 03:41:58 +0000 (03:41 +0000)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Thu, 17 Jul 2025 06:37:40 +0000 (14:37 +0800)
commit12b90ea3c2943f807b1a54d578c71839ab475be5
treead740c061b90bb93e9d86f7ed5bbf9f5c1327aa2tree
parent00a3b0eb8e4c6ee96e27759a16cb1f159021f68bcommit | diff
riscv: cpu: th1520: Limit upper RAM boundary to 4 GiB

TH1520 SoC ships DMA peripherals that could only reach the first 32-bit
range of memory, for example, the GMAC controllers. Let's limit the
usable top of RAM below 4GiB to ensure DMA allocations are accessible to
all peripherals.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/cpu/th1520/dram.c diff | blob | blame | history
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