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(parent: 9589a46) | patch
RISC-V: Add more test cases for RVV FP16
authorPan Li <pan2.li@intel.com>
Wed, 7 Jun 2023 03:41:01 +0000 (11:41 +0800)
committerPan Li <pan2.li@intel.com>
Thu, 8 Jun 2023 15:05:57 +0000 (23:05 +0800)
commit1379ae33e05c28d705f3c69a3f6c774bf6e83136
tree4ba89c705576f566b65b6242696db125f97bffadtree
parent9589a46ddadc8b93c224c3f84fa94746c04596bfcommit | diff
RISC-V: Add more test cases for RVV FP16

This patch would like to add new test cases to make sure the
RVV FP16 works well as expected.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Add new cases.
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c diff | blob | blame | history
gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c [new file with mode: 0644] blob
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