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AArch64: Improve codegen in AdvSIMD asinh
authorLuna Lamb <luna.lamb@arm.com>
Fri, 3 Jan 2025 19:00:12 +0000 (19:00 +0000)
committerWilco Dijkstra <wilco.dijkstra@arm.com>
Fri, 3 Jan 2025 21:39:56 +0000 (21:39 +0000)
commit140b985e5a2071000122b3cb63ebfe88cf21dd29
treec1a6c12c15ddf7b774559ff8bea4a05e5dced334tree
parentbb4f241dba734ddb1bd6e436b21938c1317a8fb4commit | diff
AArch64: Improve codegen in AdvSIMD asinh

Improves memory access and removes spills.
Load the polynomial evaluation coefficients into 2 vectors and use lanewise
MLAs.  Reduces MOVs 6->3 , LDR 11->5, STR/STP 2->0, ADRP 3->2.
sysdeps/aarch64/fpu/asinh_advsimd.c diff | blob | blame | history
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