]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
pinctrl: renesas: rzg2l: Add function pointer for PFC register locking
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thu, 30 May 2024 17:38:49 +0000 (18:38 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 11 Jun 2024 07:46:29 +0000 (09:46 +0200)
commit14c32dc1f63d0de865e67c04c919ae036de20f87
tree9b6e0193d57721d4a463e84da7fb65b8f365125d
parenta3a632ed87f0913779092c30bd0ea7dfd81601f3
pinctrl: renesas: rzg2l: Add function pointer for PFC register locking

On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers.
However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls
writing to both PFC and PMC registers.  Additionally, BIT(7) B0WI is
undocumented for the PWPR register on RZ/V2H(P) SoC.  To accommodate these
differences across SoC variants, introduce the pwpr_pfc_lock_unlock()
function pointer.

Note, in rzg2l_pinctrl_set_pfc_mode() the pwpr_pfc_lock_unlock(.., false)
is now called before PMC read/write and pwpr_pfc_lock_unlock(.., true) is
now called after PMC read/write this is to keep changes minimal for
RZ/V2H(P) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/pinctrl/renesas/pinctrl-rzg2l.c