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RISC-V: Fix vle constraints
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Fri, 23 Dec 2022 03:33:06 +0000 (11:33 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Fri, 23 Dec 2022 05:42:04 +0000 (13:42 +0800)
commit16eb1f43ab4e521ed4503e7766eee25da75eaeba
tree578ffb9a59bb8601cd2df6a0dd457daa707ec502tree
parenta143c3f7a61c61bb5a5e099fdb59f3adbf99b6b3commit | diff
RISC-V: Fix vle constraints

gcc/ChangeLog:

* config/riscv/vector.md: Fix contraints.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vle-constraint-1.c: New test.
gcc/config/riscv/vector.md diff | blob | blame | history
gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c [new file with mode: 0644] blob
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