]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: ICE for vlmul_ext_v intrinsic API
authorYanzhang Wang <yanzhang.wang@intel.com>
Wed, 26 Apr 2023 13:06:02 +0000 (21:06 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Tue, 2 May 2023 15:31:43 +0000 (23:31 +0800)
commit1adb1a653d6739589b12337c974c7e741cfb187c
tree1d44a3c0562631a14dadcefa3160fd9c3446044a
parent87c347c2897537a6aa391efbfc5ed00c625434fe
RISC-V: ICE for vlmul_ext_v intrinsic API

PR target/109617

gcc/ChangeLog:

* config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
gcc/config/riscv/vector-iterators.md
gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c [new file with mode: 0644]