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author | Yanzhang Wang <yanzhang.wang@intel.com> | |
Wed, 26 Apr 2023 13:06:02 +0000 (21:06 +0800) | ||
committer | Kito Cheng <kito.cheng@sifive.com> | |
Tue, 2 May 2023 15:31:43 +0000 (23:31 +0800) | ||
commit | 1adb1a653d6739589b12337c974c7e741cfb187c | |
tree | 1d44a3c0562631a14dadcefa3160fd9c3446044a | tree |
parent | 87c347c2897537a6aa391efbfc5ed00c625434fe | commit | diff |
gcc/config/riscv/vector-iterators.md | diff | blob | blame | history | |
gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c | [new file with mode: 0644] | blob |