[RISC-V] Improve sequences to generate -1, 1 in some cases.

[RISC-V] Improve sequences to generate -1, 1 in some cases.

This patch has a minor improvement to if-converted sequences based on
observations I found while evaluating another patch from Shreya to handle more
cases with zicond insns.

Specifically there is a smaller/faster way than zicond to generate a -1,1
result when the condition is testing the sign bit.

So let's consider these two tests (rv64):

long foo1 (long c, long a) { return c >= 0 ? 1 : -1; }
long foo2 (long c, long a) { return c < 0 ? -1 : 1; }

So if we right arithmetic shift c by 63 bits, that splats the sign bit across a
register giving us 0, -1 for the first test and -1, 0 for the second test.  We
then unconditionally turn on the LSB resulting in 1, -1 for the first case and
-1, 1 for the second.

This is implemented as a 4->2 splitter.  There's another pair of cases we don't
handle because we don't have 4->3 splitters.  Specifically if the true/false
values are reversed in the above examples without reversing the condition.

Raphael is playing a bit in the gimple space to see what opportunities might
exist to recognize more idioms in phiopt and generate better code earlier.  No
idea how that's likely to pan out.

This is a pretty consistent small win.  It's been through the rounds in my
tester.  Just waiting on a green light from pre-commit testing.

gcc/
	* config/riscv/zicond.md: Add new splitters to select
	1, -1 or -1, 1 based on a sign bit test.

gcc/testsuite/

	* gcc.target/riscv/nozicond-1.c: New test.
	* gcc.target/riscv/nozicond-2.c: New test.