RISC-V: Add testcases for unsigned .SAT_ADD vector form 5

RISC-V: Add testcases for unsigned .SAT_ADD vector form 5

After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 5.

Form 5:
  #define DEF_VEC_SAT_U_ADD_FMT_5(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T ret;                                                         \
        out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1;  \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
	macro for testing.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>