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(parent: dc5742b) | patch
drm/i915/ltphy: Program the VDR PLL registers for LT PHY
authorSuraj Kandpal <suraj.kandpal@intel.com>
Sat, 1 Nov 2025 03:24:57 +0000 (08:54 +0530)
committerSuraj Kandpal <suraj.kandpal@intel.com>
Sat, 1 Nov 2025 03:33:56 +0000 (09:03 +0530)
commit1dd885d5098db040e5faa5f63b301129e9a04639
tree97fcdf2e62c8b4c50ac7de14329d1ad17cc3e3f3tree | snapshot
parentdc5742b6197f1cd41302b0cc4d66a830e2b4880acommit | diff
drm/i915/ltphy: Program the VDR PLL registers for LT PHY

Fetch the tables which need to be used and program it in
the specified VDR register space. Everything is done over
the respective lanes.

Bspec: 68862, 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-10-suraj.kandpal@intel.com
drivers/gpu/drm/i915/display/intel_cx0_phy.c diff | blob | blame | history
drivers/gpu/drm/i915/display/intel_cx0_phy.h diff | blob | blame | history
drivers/gpu/drm/i915/display/intel_lt_phy.c diff | blob | blame | history
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