RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0

RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0

SiFive has define as set of flexible instruction for extending vector
coprocessor, it able to encoding opcode like .insn but with predefined
format.

List of instructions:
  sf.vc.x
  sf.vc.i
  sf.vc.vv
  sf.vc.xv
  sf.vc.iv
  sf.vc.fv
  sf.vc.vvv
  sf.vc.xvv
  sf.vc.ivv
  sf.vc.fvv
  sf.vc.vvw
  sf.vc.xvw
  sf.vc.ivw
  sf.vc.fvw
  sf.vc.v.x
  sf.vc.v.i
  sf.vc.v.vv
  sf.vc.v.xv
  sf.vc.v.iv
  sf.vc.v.fv
  sf.vc.v.vvv
  sf.vc.v.xvv
  sf.vc.v.ivv
  sf.vc.v.fvv
  sf.vc.v.vvw
  sf.vc.v.xvw
  sf.vc.v.ivw
  sf.vc.v.fvw

Spec of Xsfvcp
https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software

Co-authored-by: Hau Hsu <hau.hsu@sifive.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>