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(parent: 681e124) | patch
drm/i915/dsc: Add Selective Update register definitions
authorJouni Högander <jouni.hogander@intel.com>
Wed, 4 Mar 2026 11:30:09 +0000 (13:30 +0200)
committerJouni Högander <jouni.hogander@intel.com>
Mon, 9 Mar 2026 05:23:55 +0000 (07:23 +0200)
commit24f96d903daf3dcf8fafe84d3d22b80ef47ba493
tree02b9bc3582db7c1e59d722c38f1d679756190a59tree | snapshot
parent681e12440d8b110350a5709101169f319e10ccbbcommit | diff
drm/i915/dsc: Add Selective Update register definitions

Add definitions for DSC_SU_PARAMETER_SET_0_DSC0 and
DSC_SU_PARAMETER_SET_0_DSC1 registers. These are for Selective Update Early
Transport configuration.

Bspec: 71709
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-3-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_vdsc_regs.h diff | blob | blame | history
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