[RISC-V] Handle 32bit operands in condition for conditional moves

[RISC-V] Handle 32bit operands in condition for conditional moves

So here's the next chunk of conditional move work from Shreya.

It's been a long standing wart that the conditional move expander does not
support sub-word operands in the comparison.  Particularly since we have
support routines to handle the necessary extensions for that case.

This patch adjusts the expander to use riscv_extend_comparands rather than fail
for that case.  I've built spec2017 before/after this and we definitely get
more conditional moves and they look sensible from a performance standpoint.
None are likely hitting terribly hot code, so I wouldn't expect any performance
jumps.

Waiting on pre-commit testing to do its thing.

gcc/
	* config/riscv/riscv.cc (riscv_expand_conditional_move): Use
	riscv_extend_comparands to extend sub-word comparison arguments.

	    Co-authored-by: Jeff Law  <jlaw@ventanamicro.com>