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RISC-V: Remove masking third operand of rotate instructions
authorJoern Rennecke <joern.rennecke@embecosm.com>
Fri, 19 May 2023 22:18:42 +0000 (16:18 -0600)
committerJeff Law <jlaw@ventanamicro.com>
Fri, 19 May 2023 22:19:51 +0000 (16:19 -0600)
commit259b4b7d349dd3fd560144bd4617f526458b45dc
treeaf02364e25755ac8b817151407085277c3dac23etree
parentae2345285c28549145af203ef8161ff96e2ad877commit | diff
RISC-V: Remove masking third operand of rotate instructions

Sorry, I forgot the ChangeLog entry for my patch and missed the [v2]
part of the subject.

2023-05-18  Joern Rennecke  <joern.rennecke@embecosm.com>

gcc/ChangeLog:
* config/riscv/constraints.md (DsS, DsD): Restore agreement
with shiftm1 mode attribute.
gcc/config/riscv/constraints.md diff | blob | blame | history
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