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ASoC: amd: ps: add ZSC control register programming sequence
authorVijendar Mukunda <Vijendar.Mukunda@amd.com>
Tue, 3 Dec 2024 08:19:40 +0000 (13:49 +0530)
committerMark Brown <broonie@kernel.org>
Tue, 3 Dec 2024 14:40:59 +0000 (14:40 +0000)
commit25cd677636d316669871947639430615ff564890
treecbf4193c52a95dd795fb447a6f184e4a09efe4c3tree
parentbcbf421d2190bc4f7d3fd2cc61caf748779ee69ecommit | diff
ASoC: amd: ps: add ZSC control register programming sequence

Add ZSC Control register programming sequence for ACP D0 and D3 state
transitions for ACP6.3 platform. This will allow ACP to enter low power
state when ACP enters D3 state. When ACP enters D0 State, ZSC control
should be disabled.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20241203081940.3390281-2-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/amd/ps/pci-ps.c diff | blob | blame | history
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git