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(parent: 147a830) | patch
x86: Only align destination to 1x VEC_SIZE in memset 4x loop
authorNoah Goldstein <goldstein.w.n@gmail.com>
Wed, 1 Nov 2023 20:30:26 +0000 (15:30 -0500)
committerSunil K Pandey <skpgkp2@gmail.com>
Fri, 10 Jan 2025 16:49:42 +0000 (08:49 -0800)
commit27296daa2595d377c04fdcf1058b71f9a015fb1a
tree6bf7fb7c20dde33884017d79b85653620723c9dftree
parent147a830307f0b4a74e63789589aa68e3af875de6commit | diff
x86: Only align destination to 1x VEC_SIZE in memset 4x loop

Current code aligns to 2x VEC_SIZE. Aligning to 2x has no affect on
performance other than potentially resulting in an additional
iteration of the loop.
1x maintains aligned stores (the only reason to align in this case)
and doesn't incur any unnecessary loop iterations.
Reviewed-by: Sunil K Pandey <skpgkp2@gmail.com>
(cherry picked from commit 9469261cf1924d350feeec64d2c80cafbbdcdd4d)
sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S diff | blob | blame | history
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