]> git.ipfire.org Git - thirdparty/kernel/linux.git/commit
drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks
authorImre Deak <imre.deak@intel.com>
Mon, 17 Nov 2025 10:46:01 +0000 (12:46 +0200)
committerMika Kahola <mika.kahola@intel.com>
Wed, 19 Nov 2025 11:32:26 +0000 (13:32 +0200)
commit2a6e417907593e908d164c743f812ad6413f3d7b
treefba68257630827ed5fd9f3daff617e1b4bb9d95c
parent6b566d066c823a9ad1ec5a7043955349a71ce42b
drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks

Add the PLL hooks for the TBT PLL on MTL+. These are simple stubs
similarly to the TBT PLL on earlier platforms, since this PLL is always
on from the display POV - so no PLL enable/disable programming is
required as opposed to the non-TBT PLLs - and the clocks for different
link rates are enabled/disabled at a different level, via the
intel_encoder::enable_clock()/disable_clock() interface.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-32-mika.kahola@intel.com
drivers/gpu/drm/i915/display/intel_cx0_phy.c
drivers/gpu/drm/i915/display/intel_cx0_phy.h
drivers/gpu/drm/i915/display/intel_dpll_mgr.c