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riscv: dts: starfive: jh7110: add DMC memory controller
authorE Shattow <e@freeshell.de>
Wed, 15 Oct 2025 10:22:45 +0000 (03:22 -0700)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Tue, 28 Oct 2025 11:29:43 +0000 (19:29 +0800)
commit2b26cda14f8567680613e079e4b63c86edf4fedb
tree349f66be75481ff14315700f32362d44075e649etree
parent417ad9b0c71bd242923050173daf2e7b95e28229commit | diff
riscv: dts: starfive: jh7110: add DMC memory controller

Add JH7110 SoC DDR external memory controller.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
[ upstream commit: 7114969021ec5c4c0f3df1da3a8790f75dda92e2 ]

(cherry picked from commit 8d5c520b73b7c29b714f75e99ed48baa55fc5fa1)
dts/upstream/src/riscv/starfive/jh7110.dtsi diff | blob | blame | history
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