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dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528
authorCaleb James DeLisle <cjd@cjdns.fr>
Sat, 25 Apr 2026 17:36:41 +0000 (17:36 +0000)
committerVinod Koul <vkoul@kernel.org>
Thu, 14 May 2026 15:45:16 +0000 (21:15 +0530)
commit2cc066dbd3a211628b40967949cff2790d0f62eb
treead18a34426101a862b78bdc475da8bf5c2f88be7tree | snapshot
parent864b3617df827865a95a06f06f09a8d57a795b91commit | diff
dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528

EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY
which behaves slightly differently because one slot is Gen1/Gen2 while
the other is Gen1 only.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260425173642.406089-2-cjd@cjdns.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml [new file with mode: 0644] blob
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