[PATCH v1 1/2] RISC-V: Fix incorrect combine pattern for any_extend [PR123317]

[PATCH v1 1/2] RISC-V: Fix incorrect combine pattern for any_extend [PR123317]

From: Pan Li <pan2.li@intel.com>

The vwaddu/vwsubu wx combine patterns take the any_extend by
mistake, it is unsigned so we must leverage zero_extend here.
This PATCH would like to fix this which result in sign_extend
code pattern combine to vwaddu/vwsub.wx.

	PR target/123317

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Take zero_extend for
	both the vwaddu and vwsubu wx pattern.

Signed-off-by: Pan Li <pan2.li@intel.com>