AArch64: Add special patterns for creating DI scalar and vector constant 1 << 63...

AArch64: Add special patterns for creating DI scalar and vector constant 1 << 63 [PR109154]

This adds a way to generate special sequences for creation of constants for
which we don't have single instructions sequences which would have normally
lead to a GP -> FP transfer or a literal load.

The patch starts out by adding support for creating 1 << 63 using fneg (mov 0).

gcc/ChangeLog:

	PR tree-optimization/109154
	* config/aarch64/aarch64-protos.h (aarch64_simd_special_constant_p,
	aarch64_maybe_generate_simd_constant): New.
	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VQMOV:mode>,
	*aarch64_simd_mov<VDMOV:mode>): Add new coden for special constants.
	* config/aarch64/aarch64.cc (aarch64_extract_vec_duplicate_wide_int):
	Take optional mode.
	(aarch64_simd_special_constant_p,
	aarch64_maybe_generate_simd_constant): New.
	* config/aarch64/aarch64.md (*movdi_aarch64): Add new codegen for
	special constants.
	* config/aarch64/constraints.md (Dx): new.

gcc/testsuite/ChangeLog:

	PR tree-optimization/109154
	* gcc.target/aarch64/fneg-abs_1.c: Updated.
	* gcc.target/aarch64/fneg-abs_2.c: Updated.
	* gcc.target/aarch64/fneg-abs_4.c: Updated.
	* gcc.target/aarch64/dbl_mov_immediate_1.c: Updated.