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dt-bindings: pinctrl: document polarfire soc iomux0 pinmux
authorConor Dooley <conor.dooley@microchip.com>
Thu, 23 Oct 2025 17:14:59 +0000 (18:14 +0100)
committerLinus Walleij <linus.walleij@linaro.org>
Fri, 24 Oct 2025 09:08:25 +0000 (11:08 +0200)
commit2f0073afd9bf88263c3d5136680a0e33a413383f
tree27c773ee125145d4ed987bc73763c63ea8e59fc4tree | snapshot
parent38cf9d6413142290316776c80f19eb92a4e19a9fcommit | diff
dt-bindings: pinctrl: document polarfire soc iomux0 pinmux

On Polarfire SoC, iomux0 is responsible for routing functions to either
Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they
can either interface with custom RTL or be routed to the FPGA fabric's
IOs. Document it.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml [new file with mode: 0644] blob
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml diff | blob | blame | history
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