RISC-V: Refine the mask generation for vec_init case 2

RISC-V: Refine the mask generation for vec_init case 2

Update in v2:
1. Add more test cases for fixed-vlmax.
2, Add test cases for vls mode.

Original log:

We take vec_init element int mode when generate the mask for
case 2. But actually we don't need as many bits as the element.
The extra bigger mode may introduce some unnecessary insns.
For example as below code:

typedef int64_t v16di __attribute__ ((vector_size (16 * 8)));

void __attribute__ ((noinline, noclone))
  foo (int64_t *out, int64_t x, int64_t y)
{
  v16di v = {y, x, y, x, y, x, y, x, y, x, y, x, y, x, y, x};
  *(v16di *) out = v;
}

We will have VDImode when generate the 0b0101010101010101 mask but
actually VHImode is good enough here. This patch would like to
refine the mask generation to avoid:
1. Unnecessary scalar to generate big constant mask.
2. Unnecessary vector insn to v0 mask.

Before this patch:
foo:
  li      a5,-1431654400
  li      a4,-1431654400               <== unnecessary insn
  addi    a5,a5,-1365                  <== unnecessary insn
  addi    a4,a4,-1366
  slli    a5,a5,32                     <== unnecessary insn
  add     a5,a5,a4                     <== unnecessary insn
  vsetivli        zero,16,e64,m8,ta,ma
  vmv.v.x v8,a2
  vmv.s.x v16,a5
  vmv1r.v v0,v16                       <== unnecessary insn
  vmerge.vxm      v8,v8,a1,v0
  vse64.v v8,0(a0)
  ret

After this patch:
foo:
  li      a5,-20480
  addiw   a5,a5,-1366
  vsetivli        zero,16,e64,m8,ta,ma
  vmv.s.x v0,a5
  vmv.v.x v8,a2
  vmerge.vxm      v8,v8,a1,v0
  vs8r.v  v8,0(a0)
  ret

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (rvv_builder::get_merge_scalar_mask):
	Add inner_mode mask arg for mask int mode.
	(get_repeating_sequence_dup_machine_mode): Add mask_bit_mode arg
	to get the good enough vector int mode on precision.
	(expand_vector_init_merge_repeating_sequence): Pass required args
	to above func.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-10.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-11.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-12.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-13.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-14.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-15.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-6.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-7.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-8.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-9.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-0.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-4.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-5.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-6.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-7.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/init-repeat-sequence-8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>