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riscv: traps_misaligned: properly sign extend value in misaligned load handler
authorAndreas Schwab <schwab@suse.de>
Thu, 10 Jul 2025 13:32:18 +0000 (15:32 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 24 Jul 2025 06:58:37 +0000 (08:58 +0200)
commit31e9cd03fa002aac4b68e5cd98ffa51580c778a3
tree2949215d2d0e15799760734af41e3ee44ed33ac7tree | snapshot
parent7162e32462c8d4627b847b1b555d325fd44a48b2commit | diff
riscv: traps_misaligned: properly sign extend value in misaligned load handler

[ Upstream commit b3510183ab7d63c71a3f5c89043d31686a76a34c ]

Add missing cast to signed long.

Signed-off-by: Andreas Schwab <schwab@suse.de>
Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/riscv/kernel/traps_misaligned.c diff | blob | blame | history
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git