Power PC Add support for ISA 3.0, part 1

Power PC Add support for ISA 3.0, part 1

The Floating-point condition code bits FPCC is bits[15:12] of the FPSCR.
The instructions fcmpu, fcmpo, dcmpu, dcmpq, dtstdc, dtstdcq, xscmpodq
and xscmpudq set the FPCC bits in addition to the BE field of the CC
register.  This support is needed by the ISA 3.0 instructions to be added.

Added support to emulate the modsw, moduw, modsd, modud, extswsli,
maddld, maddhd, maaddhdu, xxperm, xxpermr, vabsdub, vabsduh, vabsduw,
mtvsrws, xxextractuw, xxinsertw, xxspltib, xxbrh, xxbrw, xxbrd, xxbrq,
vpermr, vextractub, vextractuh, vextractuw, vextractd, vinsertb, vinserth,
vinsertw, vinsertd, lxvwsx, stxvb16x, stxvx, lxvb16x, lxvh8x, lxvx
instructions.

valgrind bugzilla 359767

git-svn-id: svn://svn.valgrind.org/vex/trunk@3214