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riscv: add parsing for Zaamo and Zalrsc extensions
authorClément Léger <cleger@rivosinc.com>
Wed, 19 Jun 2024 15:39:09 +0000 (17:39 +0200)
committerAlexandre Ghiti <alexghiti@rivosinc.com>
Wed, 19 Mar 2025 12:03:45 +0000 (12:03 +0000)
commit35173b666a16ce631da9d70cd1b376162d9dea53
tree32dbf66403d85e4e198765669c5596038df7771ctree
parenta65e0f67da24d1bff0dc679a018ced26d1952683commit | diff
riscv: add parsing for Zaamo and Zalrsc extensions

These 2 new extensions are actually a subset of the A extension which
provides atomic memory operations and load-reserved/store-conditional
instructions.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240619153913.867263-3-cleger@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
arch/riscv/include/asm/hwcap.h diff | blob | blame | history
arch/riscv/kernel/cpufeature.c diff | blob | blame | history
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