RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1

RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1

After the middle-end supported the vector mode of .SAT_ADD,  add more
testcases to ensure the correctness of RISC-V backend for form 1.  Aka:

Form 1:
  #define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)                          \
  T __attribute__((noinline))                                          \
  vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      out[i] = (T)(in[i] + IMM) >= in[i] ? (in[i] + IMM) : -1;         \
  }

DEF_VEC_SAT_U_ADD_IMM_FMT_1 (uint64_t, 9)

Passed the fully rv64gcv regression tests.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add help
	test macro.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>