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ASoC: tegra: CIF: Add Tegra264 support
authorSheetal <sheetal@nvidia.com>
Mon, 12 May 2025 05:17:39 +0000 (05:17 +0000)
committerMark Brown <broonie@kernel.org>
Thu, 22 May 2025 10:02:05 +0000 (11:02 +0100)
commit35c0d1de8e669878797e40cc625f4bdc37c3e084
treeabeee239656b5dfe0599f32bb8010ec4c68a5725tree | snapshot
parent628dafc476eb658544ad6b5b3592bfcd82597051commit | diff
ASoC: tegra: CIF: Add Tegra264 support

In Tegra264, the CIF register data bit positions are changed for I2S,
AMX, ADX and ADMAIF AHUB modules, as they now support a maximum of
32 channels. tegra264_set_cif API added to set the CIF for IPs supporting
32 channels.

Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-4-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/tegra/tegra_cif.h diff | blob | blame | history
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