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(parent: 4aebe73) | patch
drm/amd/display: bypass post csc for additional color spaces in dcn42
authorRoman Li <Roman.Li@amd.com>
Mon, 13 Apr 2026 21:32:55 +0000 (17:32 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 17 Apr 2026 19:41:15 +0000 (15:41 -0400)
commit35e86e6a54e82e3624e9abdad61c8d4b0f764396
treefe315e04230bf082b90dbf4baeb83882e2d43c75tree | snapshot
parent4aebe73f44bb57ccc8bcdba15a2d56ebfe452d4dcommit | diff
drm/amd/display: bypass post csc for additional color spaces in dcn42

[Why]
This aligns dcn42 with:
"drm/amd/display: bypass post csc for additional color spaces in dal"

[How]
Apply the same post csc bypass logic to dcn42 dpp using the
helper function.

Signed-off-by: Roman Li <roman.li@amd.com>
Acked-by: Chenyu Chen <chen-yu.chen@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c diff | blob | blame | history
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