RISC-V: Adding cost model for zilsd

RISC-V: Adding cost model for zilsd

Motivation of this patch is we want to use ld/sd if possible when zilsd
is enabled, however the subreg pass may split that into two lw/sw
instructions because the cost, and it only check cost for 64 bits reg move,
that's why we need adjust cost for 64 bit reg move as well.

However even we adjust the cost model, 64 bit shift still use 32 bit
load because it already got split at expand time, this may need to fix
on the expander side, and this apparently need few more time to
investigate, so I just added a testcase with XFAIL to show the current behavior,
and we can fix that...when we have time.

For long term, we may adding a new field to riscv_tune_param to control
the cost model for that.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_cost_model): Add cost model for
	zilsd.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zilsd-code-gen-split-subreg-1.c: New test.
	* gcc.target/riscv/zilsd-code-gen-split-subreg-2.c: New test.