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clk: spacemit: ccu_pll: add plla type clock
authorYixun Lan <dlan@gentoo.org>
Mon, 27 Oct 2025 13:41:24 +0000 (21:41 +0800)
committerYixun Lan <dlan@gentoo.org>
Fri, 9 Jan 2026 02:29:10 +0000 (10:29 +0800)
commit3a086236c600739d6653c0405d86aff7d6f03c06
tree520093bed874c9cabb09d0eb29148033b966a3c9tree
parentace73b7e27633ec770cfb24cd4ff42c24815a9aacommit | diff
clk: spacemit: ccu_pll: add plla type clock

Introduce a new clock PLLA for SpacemiT's K3 SoC which has a different
register layout comparing to previous PPL type. And, It is configured
by swcr1, swcr3 and swcr2 BIT[15:8].

Link: https://lore.kernel.org/r/20260108-k3-clk-v5-3-42a11b74ad58@gentoo.org
Signed-off-by: Yixun Lan <dlan@gentoo.org>
drivers/clk/spacemit/ccu_common.h diff | blob | blame | history
drivers/clk/spacemit/ccu_pll.c diff | blob | blame | history
drivers/clk/spacemit/ccu_pll.h diff | blob | blame | history
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