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ACPICA: Replace TPRn Base and Limit registers
authorMichal Camacho Romero <michal.camacho.romero@intel.com>
Wed, 14 Jan 2026 12:39:10 +0000 (13:39 +0100)
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>
Thu, 15 Jan 2026 17:17:50 +0000 (18:17 +0100)
commit3b8907925a7964903955b59d974d98c7ae707d7a
tree50811fa6c156efc13e615f551d26e3bcfcdc5df0tree
parent099b050699c739797f6dd2bf47f6e15f11504db4commit | diff
ACPICA: Replace TPRn Base and Limit registers

Replace TPRn Base and Limit registers with compatible bitmasks for them.

Link: https://github.com/acpica/acpica/commit/be91c5813936
Signed-off-by: Michal Camacho Romero <michal.camacho.romero@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://patch.msgid.link/1871109.TLkxdtWsSY@rafael.j.wysocki
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