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arm64: dts: socfpga: agilex5: Add L2 and L3 cache
authorAdrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Wed, 15 Oct 2025 02:12:42 +0000 (10:12 +0800)
committerDinh Nguyen <dinguyen@kernel.org>
Tue, 4 Nov 2025 21:25:44 +0000 (15:25 -0600)
commit3e99d51aaaba3ed3f092f635ad053fe1ca5953ff
tree4cbb0279f419608187fa4ece839b254454beeb37tree | snapshot
parent2f6da95cfbafce1fc92f8f37944356c248bec36dcommit | diff
arm64: dts: socfpga: agilex5: Add L2 and L3 cache

Add L2 and L3 cache nodes to the device tree to resolve the
"unable to detect cache hierarchy" warning reported by cacheinfo.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi diff | blob | blame | history
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