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target/loongarch: add msg interrupt CSR registers
authorSong Gao <gaosong@loongson.cn>
Tue, 16 Sep 2025 12:21:03 +0000 (20:21 +0800)
committerSong Gao <gaosong@loongson.cn>
Sun, 28 Sep 2025 09:31:04 +0000 (17:31 +0800)
commit3ff989d566ec880a5d06de7bb65d3dc35fc3b63b
tree7e1ccab62e5a6a151c0b858a6d2ca17bb8dbd252tree
parent4d4baab24179b51072f5e182aa41d44306ed593ccommit | diff
target/loongarch: add msg interrupt CSR registers

include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.

Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20250916122109.749813-6-gaosong@loongson.cn>
target/loongarch/cpu-csr.h diff | blob | blame | history
target/loongarch/cpu.h diff | blob | blame | history
target/loongarch/machine.c diff | blob | blame | history
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