]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/loongarch: Add sc.q instructions
authorJiajie Chen <c@jia.je>
Wed, 19 Nov 2025 12:30:57 +0000 (20:30 +0800)
committerSong Gao <gaosong@loongson.cn>
Tue, 10 Feb 2026 02:48:20 +0000 (10:48 +0800)
commit424227ff546b8d90471b2baea0c822fabb24df97
tree66a6629bd5ae05d74ac6e60185e3b3e39b206e75
parent6e533aca52358dae53d6f4b9db00afb4e50b1e80
target/loongarch: Add sc.q instructions

Add the sc.q instruction in LoongArch v1.1, guarded by CPUCFG2.SCQ. It
is implemented by reading 128bit data (llval + llval_high) in ll.d when
aligned to 16B boundary, and cmpxchg 128bit in sc.q. If ld.d
matches the higher part of the 128bit, its data is taken from
llval_high.

Expected assembly sequence:

ll.d lo, base, 0
ld.d hi, base, 8
sc.q lo, hi, base

Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
target/loongarch/cpu.h
target/loongarch/disas.c
target/loongarch/insns.decode
target/loongarch/tcg/insn_trans/trans_atomic.c.inc
target/loongarch/tcg/insn_trans/trans_memory.c.inc
target/loongarch/tcg/translate.c
target/loongarch/translate.h