RISC-V: Add testcase for unsigned scalar SAT_MUL form 6

RISC-V: Add testcase for unsigned scalar SAT_MUL form 6

The form 6 of unsigned scalar SAT_MUL has supported from the
previous change.  Thus, add the test cases to make sure it
works well.

The below test suites are passed for this patch series.
 * The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat/sat_u_mul-7-u16-from-u128.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u16-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u16-from-u64.rv32.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u16-from-u64.rv64.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u32-from-u128.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u32-from-u64.rv32.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u32-from-u64.rv64.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u64-from-u128.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u8-from-u128.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u8-from-u16.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u8-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u8-from-u64.rv32.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-7-u8-from-u64.rv64.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-run-7-u16-from-u128.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-run-7-u16-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-run-7-u16-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-run-7-u32-from-u128.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-run-7-u32-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-run-7-u64-from-u128.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-run-7-u8-from-u128.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-run-7-u8-from-u16.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-run-7-u8-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_mul-run-7-u8-from-u64.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>