iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms

iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms

The NXP S32G2 and S32G3 platforms integrate a successive approximation
register (SAR) ADC. Two instances are available, each providing 8
multiplexed input channels with 12-bit resolution. The conversion rate
is up to 1 Msps depending on the configuration and sampling window.

The SAR ADC supports raw, buffer, and trigger modes. It can operate
in both single-shot and continuous conversion modes, with optional
hardware triggering through the cross-trigger unit (CTU) or external
events. An internal prescaler allows adjusting the sampling clock,
while per-channel programmable sampling times provide fine-grained
trade-offs between accuracy and latency. Automatic calibration is
performed at probe time to minimize offset and gain errors.

All modes have been validated on the S32G274-RDB2 platform using an
externally generated square wave captured by the ADC. Tests covered
buffered streaming via IIO, trigger synchronization, and accuracy
verification against a precision laboratory signal source.

One potential scenario, not detected during testing, is that in some
corner cases the DMA may already have been armed for the next
transfer, which can lead dmaengine_tx_status() to return an incorrect
residue.  The callback_result() operation—intended to supply the
residue directly and eliminate the need to call
dmaengine_tx_status()—also does not work.  Attempting to use
dmaengine_pause() and dmaengine_resume() to prevent the residue from
being updated does not work either.

This potential scenario should apply to any driver using cyclic DMA.
However, no current driver actually handles this case, and they all rely
on the same acquisition routine (e.g., the STM32 implementation).
The NXP SAR acquisition routine has been used in production for several
years, which is a good indication of its robustness.

As the IIO is implementing the cyclic DMA support API, it is not worth
to do more spins to the current routine as it will go away when the
new API will be available.

The driver is derived from the BSP implementation and has been partly
rewritten to comply with upstream requirements. For this reason, all
contributors to the original code are listed as co-developers.

Originally-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
Co-developed-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com>
Co-developed-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Co-developed-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com>
Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>