]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
arm64: dts: rockchip: Move uart5 pin configuration to px30 ringneck SoM
authorLukasz Czechowski <lukasz.czechowski@thaumatec.com>
Tue, 21 Jan 2025 12:56:03 +0000 (13:56 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 27 Feb 2025 12:34:19 +0000 (04:34 -0800)
commit47d363a6669b6028bb1f4eac4fe8b44d45d59dbc
tree561cd9f53126d6105cd975cc484e2f9023d59574
parent8f27fa1ef4fdef56c86662ba723198eb5f47af65
arm64: dts: rockchip: Move uart5 pin configuration to px30 ringneck SoM

commit 4eee627ea59304cdd66c5d4194ef13486a6c44fc upstream.

In the PX30-uQ7 (Ringneck) SoM, the hardware CTS and RTS pins for
uart5 cannot be used for the UART CTS/RTS, because they are already
allocated for different purposes. CTS pin is routed to SUS_S3#
signal, while RTS pin is used internally and is not available on
Q7 connector. Move definition of the pinctrl-0 property from
px30-ringneck-haikou.dts to px30-ringneck.dtsi.

This commit is a dependency to next commit in the patch series,
that disables DMA for uart5.

Cc: stable@vger.kernel.org
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com>
Link: https://lore.kernel.org/r/20250121125604.3115235-2-lukasz.czechowski@thaumatec.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi