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author	Juzhe-Zhong <juzhe.zhong@rivai.ai>
	Mon, 11 Sep 2023 03:22:26 +0000 (11:22 +0800)
committer	Lehua Ding <lehua.ding@rivai.ai>
	Mon, 11 Sep 2023 03:25:51 +0000 (11:25 +0800)
commit	4ab2520ec424fa097ec839f2cde33522b220e93a
tree	f8d3d11e27308e970822246fae7e004d1ac7d366	tree
parent	190cf0ce8f4c141ac5b42d53b9ddeba367495333	commit \| diff

RISC-V: Add missing VLS mask bool mode reg -> reg patterns

Committed.

gcc/ChangeLog:

* config/riscv/autovec-vls.md (*mov<mode>_vls): New pattern.
* config/riscv/vector-iterators.md: New iterator

gcc/config/riscv/autovec-vls.md		diff \| blob \| blame \| history
gcc/config/riscv/vector-iterators.md		diff \| blob \| blame \| history

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