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Merge r1742 and r1743 (x86 and amd64 front ends: synthesise SIGILL in
authorJulian Seward <jseward@acm.org>
Sun, 29 Apr 2007 10:20:05 +0000 (10:20 +0000)
committerJulian Seward <jseward@acm.org>
Sun, 29 Apr 2007 10:20:05 +0000 (10:20 +0000)
commit4b3002e72db1e5f2b3b363e3b46556e3bbb786ac
treea5f69932393198da85c5bb767eddf78b96c551aftree
parentfb8d9a838df3af1162aba8411e60124585b10075commit | diff
Merge r1742 and r1743 (x86 and amd64 front ends: synthesise SIGILL in
the normal way for some obscure invalid instruction cases, rather than
asserting, as happened in #143079 and #142279.)

git-svn-id: svn://svn.valgrind.org/vex/branches/VEX_3_2_BRANCH@1755
VEX/priv/guest-amd64/toIR.c diff | blob | blame | history
VEX/priv/guest-x86/toIR.c diff | blob | blame | history
Mirror of https://sourceware.org/git/valgrind.git