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drm/i915: Reoder BDW+ EU/slice fuse bits
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 11 Feb 2025 23:19:38 +0000 (01:19 +0200)
committerAndi Shyti <andi.shyti@linux.intel.com>
Tue, 4 Mar 2025 14:39:37 +0000 (15:39 +0100)
commit4cdaba1bb02392422ebf6aadff8d7fb8b9049d2f
tree0981d99373e6f4e5232d983ba9bebbcd2503cdf5tree | snapshot
parentd75131164e398750269487cb72c132c39997956acommit | diff
drm/i915: Reoder BDW+ EU/slice fuse bits

We customarily define the bits of a register in big endian
order. Reorder the BDW+ fuse bits to match.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-11-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/gt/intel_gt_regs.h diff | blob | blame | history
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