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(parent: 55b5d19) | patch
spi: spi-cadence: supports transmission with bits_per_word of 16 and 32
authorJun Guo <jun.guo@cixtech.com>
Fri, 31 Oct 2025 07:30:02 +0000 (15:30 +0800)
committerMark Brown <broonie@kernel.org>
Thu, 13 Nov 2025 18:56:49 +0000 (18:56 +0000)
commit4e00135b2dd1d7924a58bffa551b6ceb3bd836f2
tree60193a4a41dad5fc9bd9cfae71d6c7b9f1abc13atree | snapshot
parent55b5d192bab5e152bda8f8cefe837c4ed0ec60c5commit | diff
spi: spi-cadence: supports transmission with bits_per_word of 16 and 32

The default FIFO data width of the Cadence SPI IP is 8 bits, but
the hardware supports configurations of 16 bits and 32 bits.
This patch enhances the driver to support communication with both
16-bits and 32-bits FIFO data widths.

Signed-off-by: Jun Guo <jun.guo@cixtech.com>
Link: https://patch.msgid.link/20251031073003.3289573-3-jun.guo@cixtech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-cadence.c diff | blob | blame | history
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