]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
drm/dp: Change AUX DPCD probe address from DPCD_REV to LANE0_1_STATUS
authorImre Deak <imre.deak@intel.com>
Sat, 23 Aug 2025 13:16:59 +0000 (09:16 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 28 Aug 2025 14:26:16 +0000 (16:26 +0200)
commit4f546a77671076a0a49c08b4c6a7d0888d72f7d2
tree7b1193ecc074296b69b73b7049f2b7d48013ffba
parent48b5547d896c9e353ecbe12eb63376d33f81bc19
drm/dp: Change AUX DPCD probe address from DPCD_REV to LANE0_1_STATUS

[ Upstream commit a40c5d727b8111b5db424a1e43e14a1dcce1e77f ]

Reading DPCD registers has side-effects in general. In particular
accessing registers outside of the link training register range
(0x102-0x106, 0x202-0x207, 0x200c-0x200f, 0x2216) is explicitly
forbidden by the DP v2.1 Standard, see

3.6.5.1 DPTX AUX Transaction Handling Mandates
3.6.7.4 128b/132b DP Link Layer LTTPR Link Training Mandates

Based on my tests, accessing the DPCD_REV register during the link
training of an UHBR TBT DP tunnel sink leads to link training failures.

Solve the above by using the DP_LANE0_1_STATUS (0x202) register for the
DPCD register access quirk.

Cc: <stable@vger.kernel.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/20250605082850.65136-2-imre.deak@intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/display/drm_dp_helper.c