i386: Use Shuffles instead of shifts for Reduction in AMD znver4/5

i386: Use Shuffles instead of shifts for Reduction in AMD znver4/5

In AMD znver4, znver5 targets vpshufd, vpsrldq have latencies 1,2 and
throughput 4 (2 for znver4),2 respectively. It is better to generate
shuffles instead of shifts wherever possible. In this patch we try to
generate appropriate shuffle instruction to copy higher half to lower
half instead of a simple right shift during horizontal vector reduction.

gcc/ChangeLog:

	* config/i386/i386-expand.cc (emit_reduc_half): Use shuffles to
	generate reduc half for V4SI, similar modes.
	* config/i386/i386.h (TARGET_SSE_REDUCTION_PREFER_PSHUF): New Macro.
	* config/i386/x86-tune.def (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF):
	New tuning.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/reduc-pshuf.c: New test.