RISC-V: Add testcases for form 4 of signed scalar SAT_ADD

RISC-V: Add testcases for form 4 of signed scalar SAT_ADD

Form 4:
  #define DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)           \
  T __attribute__((noinline))                            \
  sat_s_add_##T##_fmt_4 (T x, T y)                       \
  {                                                      \
    T sum;                                               \
    bool overflow = __builtin_add_overflow (x, y, &sum); \
    return !overflow ? sum : x < 0 ? MIN : MAX;          \
  }

DEF_SAT_S_ADD_FMT_4 (int64_t, uint64_t, INT64_MIN, INT64_MAX)

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat_s_add-13.c: New test.
	* gcc.target/riscv/sat_s_add-14.c: New test.
	* gcc.target/riscv/sat_s_add-15.c: New test.
	* gcc.target/riscv/sat_s_add-16.c: New test.
	* gcc.target/riscv/sat_s_add-run-13.c: New test.
	* gcc.target/riscv/sat_s_add-run-14.c: New test.
	* gcc.target/riscv/sat_s_add-run-15.c: New test.
	* gcc.target/riscv/sat_s_add-run-16.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>