RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3

RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3

This patch would like to add test cases for the unsigned scalar quad and
oct .SAT_TRUNC form 3.  Aka:

Form 3:
  #define DEF_SAT_U_TRUC_FMT_3(NT, WT)     \
  NT __attribute__((noinline))             \
  sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
  {                                        \
    WT max = (WT)(NT)-1;                   \
    return x <= max ? (NT)x : (NT) max;    \
  }

QUAD:
DEF_SAT_U_TRUC_FMT_3 (uint16_t, uint64_t)
DEF_SAT_U_TRUC_FMT_3 (uint8_t, uint32_t)

OCT:
DEF_SAT_U_TRUC_FMT_3 (uint8_t, uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_u_trunc-16.c: New test.
	* gcc.target/riscv/sat_u_trunc-17.c: New test.
	* gcc.target/riscv/sat_u_trunc-18.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-16.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-17.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-18.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>