]> git.ipfire.org Git - thirdparty/kernel/linux.git/commit
dt-bindings: pinctrl: renesas: Document RZ/T2H and RZ/N2H SoCs
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Fri, 8 Aug 2025 13:30:15 +0000 (14:30 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 11 Aug 2025 13:47:03 +0000 (15:47 +0200)
commit5293e8f2a854344ef9aba2391b44c7a437889ebb
tree31bfe4065545c205db5ac3acec2699ed980fe280
parent8a5a0294f40a50e5be83e9b7ebbc15b546f64e41
dt-bindings: pinctrl: renesas: Document RZ/T2H and RZ/N2H SoCs

Document the pin and GPIO controller IP for the Renesas RZ/T2H
(R9A09G077) and RZ/N2H (R9A09G087) SoCs, and add the shared DTSI header
file used by both the bindings and the driver.

The RZ/T2H SoC supports 729 pins, while RZ/N2H supports 576 pins.
Both share the same controller architecture; separate compatible strings
are added for each SoC to distinguish them.

Co-developed-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250808133017.2053637-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml [new file with mode: 0644]
include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h [new file with mode: 0644]