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dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Sat, 26 Oct 2024 15:43:31 +0000 (18:43 +0300)
committerBjorn Andersson <andersson@kernel.org>
Mon, 4 Nov 2024 04:04:22 +0000 (22:04 -0600)
commit53b3e2e0c9a36263be6874203c68bd7bd104663f
treea1fbe8b983289835848f66a904ce061acada98aftree | snapshot
parentd088afa7de3cbe689954dad49e7058d2c4b8944ccommit | diff
dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P

Describe the last level cache controller on the SAR2130P and SAR1130P
platforms. They have 2 banks and also a separate register set to control
scratchpad slice.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241026-sar2130p-llcc-v3-1-2a58fa1b4d12@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Documentation/devicetree/bindings/cache/qcom,llcc.yaml diff | blob | blame | history
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